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[libretiny] Fix RTL8710B IRAM_ATTR section being dropped from flashed image (#16616)
This commit is contained in:
J. Nick Koston
@@ -11,11 +11,19 @@
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#include "esphome/core/time_64.h"
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// IRAM_ATTR places a function in executable RAM so it is callable from an
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// ISR even while flash is busy (XIP stall, OTA, logger flash write).
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// Each family uses a section its stock linker already routes to RAM:
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// RTL8710B → .image2.ram.text, RTL8720C → .sram.text. LN882H is the
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// exception: its stock linker has no matching glob, so patch_linker.py
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// injects KEEP(*(.sram.text*)) into .flash_copysection at pre-link.
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// ISR even while flash is busy (XIP stall, OTA, logger flash write). All
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// LibreTiny families that need it share the same .sram.text input section
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// name; how that section is routed into RAM differs per family:
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// RTL8720C: stock linker consumes *(.sram.text*) into .ram.code_text.
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// RTL8710B: patch_linker.py.script injects KEEP(*(.sram.text*)) at the
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// top of .ram_image2.data (which IS in ltchiptool's
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// sections_ram). The stock linker has KEEP(*(.image2.ram.text*))
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// in .ram_image2.text but that output section is NOT in
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// ltchiptool's AmebaZ elf2bin sections_ram list, so code routed
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// there is dropped from the flashed binary.
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// LN882H: patch_linker.py.script injects KEEP(*(.sram.text*)) into
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// .flash_copysection (> RAM0 AT> FLASH), after KEEP(*(.vectors))
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// so the Cortex-M4 vector table stays 512-byte-aligned for VTOR.
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//
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// BK72xx (all variants) are left as a no-op: their SDK wraps flash
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// operations in GLOBAL_INT_DISABLE() which masks FIQ + IRQ at the CPU for
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@@ -26,13 +34,7 @@
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// layer.
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#if defined(USE_BK72XX)
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#define IRAM_ATTR
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#elif defined(USE_LIBRETINY_VARIANT_RTL8710B)
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// Stock linker consumes *(.image2.ram.text*) into .ram_image2.text (> BD_RAM).
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#define IRAM_ATTR __attribute__((noinline, section(".image2.ram.text")))
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#else
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// RTL8720C: stock linker consumes *(.sram.text*) into .ram.code_text.
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// LN882H: patch_linker.py.script injects *(.sram.text*) into
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// .flash_copysection (> RAM0 AT> FLASH).
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#define IRAM_ATTR __attribute__((noinline, section(".sram.text")))
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#endif
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#define PROGMEM
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@@ -6,12 +6,18 @@ import re
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import subprocess
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# ESPHome marks ISR code IRAM_ATTR, which on LibreTiny maps to a per-family
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# section routed into RAM-executable memory (see esphome/core/hal.h).
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# section routed into RAM-executable memory (see esphome/core/hal.h). The
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# input section name is always .sram.text; only the output section it lands
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# in differs per family.
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#
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# This script is NOT loaded on BK72xx (IRAM_ATTR is a no-op there; the SDK
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# masks FIQ+IRQ around flash writes). On the remaining families:
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# - RTL8710B: hal.h uses section(".image2.ram.text"); stock linker consumes it.
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# - RTL8720C: hal.h uses section(".sram.text"); stock linker consumes it.
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# - RTL8720C: stock linker consumes *(.sram.text*) into .ram.code_text.
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# - RTL8710B: stock linker has KEEP(*(.image2.ram.text*)) in .ram_image2.text,
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# but ltchiptool's AmebaZ elf2bin (soc/ambz/binary.py) does NOT list
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# .ram_image2.text in sections_ram, so code there is silently dropped from
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# the flashed image. Inject KEEP(*(.sram.text*)) at the top of
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# .ram_image2.data (which IS extracted) instead.
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# - LN882H: stock linker has no glob for ".sram.text", so we inject
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# KEEP(*(.sram.text*)) into ".flash_copysection" (> RAM0 AT> FLASH)
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# immediately after KEEP(*(.vectors)), so the vector table stays at
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@@ -34,6 +40,20 @@ _KEEP_LINE = (
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# aligned address; injecting before the vectors would push them to an
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# unaligned offset and mis-route every IRQ handler.
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_LN_COPY = re.compile(r"(KEEP\(\*\(\.vectors\)\)[^\n]*\n)")
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# Inject at the top of .ram_image2.data, before __data_start__ so our code
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# does not fall inside the data range markers. .ram_image2.data is one of the
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# sections ltchiptool's AmebaZ elf2bin extracts; BD_RAM is rwx so the code is
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# executable. AmbZ has no C runtime .data copy loop (the bootloader loads
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# image2 into BD_RAM whole) so the inline code is not clobbered after boot.
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#
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# The regex is intentionally strict (no attribute / ALIGN between the section
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# name and the opening brace, brace on its own line). If a future AmbZ SDK
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# linker template changes this format, _pre_link raises RuntimeError on the
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# unpatched .ld file(s), and the RTL8710B CI compile job in
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# tests/test_build_components fails on the PR, surfacing the mismatch loudly
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# rather than silently shipping a binary with IRAM_ATTR code dropped from
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# one or both OTA slots.
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_AMBZ_DATA = re.compile(r"(\.ram_image2\.data\s*:\s*\n?\s*\{\s*\n)")
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def _detect(env):
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@@ -71,12 +91,11 @@ def _inject_keep(host_section):
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# Variants not listed here intentionally have no .ld patcher:
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# - RTL8710B: hal.h uses section(".image2.ram.text") which the stock linker
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# already routes into .ram_image2.text (> BD_RAM).
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# - RTL8720C: stock linker already consumes *(.sram.text*).
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# - RTL8720C: stock linker already consumes *(.sram.text*) into .ram.code_text.
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# - BK72xx (all): SDK masks FIQ+IRQ around flash writes, IRAM_ATTR is no-op.
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_PATCHERS_BY_VARIANT = {
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"LN882H": (_inject_keep(_LN_COPY),),
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"RTL8710B": (_inject_keep(_AMBZ_DATA),),
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}
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@@ -87,13 +106,14 @@ def _patchers_for(variant):
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def _pre_link(target, source, env):
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build_dir = env.subst("$BUILD_DIR")
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ld_files = [f for f in os.listdir(build_dir) if f.endswith(".ld")]
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patched = 0
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patched = []
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unpatched = []
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for name in ld_files:
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path = os.path.join(build_dir, name)
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with open(path, "r", encoding="utf-8") as fh:
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original = fh.read()
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if _MARKER in original:
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patched += 1
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patched.append(name)
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continue
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content = original
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for fn in _patchers:
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@@ -102,7 +122,9 @@ def _pre_link(target, source, env):
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with open(path, "w", encoding="utf-8") as fh:
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fh.write(content)
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print("ESPHome: patched {} for IRAM_ATTR placement".format(name))
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patched += 1
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patched.append(name)
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else:
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unpatched.append(name)
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if not patched:
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raise RuntimeError(
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"ESPHome: no .ld in {} was patched for IRAM_ATTR. Update the "
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@@ -110,6 +132,20 @@ def _pre_link(target, source, env):
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build_dir
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)
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)
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# Every .ld in the build must be patched. RTL8710B generates one .ld per
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# OTA slot (xip1, xip2); if only one matches, the unpatched slot would
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# ship with IRAM_ATTR code dropped to zeros and brick the device on the
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# boot after an OTA into that slot.
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if unpatched:
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raise RuntimeError(
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"ESPHome: {} of {} .ld file(s) in {} were not patched for "
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"IRAM_ATTR: {}. The regex in patch_linker.py.script "
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"(_PATCHERS_BY_VARIANT[{!r}]) matched the others but not "
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"these. Update the regex to cover all linker scripts.".format(
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len(unpatched), len(ld_files), build_dir,
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", ".join(unpatched), _variant,
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)
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)
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# Substrings matched against demangled names as a fallback on RTL8720C,
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