diff --git a/esphome/components/libretiny/hal.h b/esphome/components/libretiny/hal.h
index 9c512504b7..01a7b5450b 100644
--- a/esphome/components/libretiny/hal.h
+++ b/esphome/components/libretiny/hal.h
@@ -11,11 +11,19 @@
 #include "esphome/core/time_64.h"
 
 // IRAM_ATTR places a function in executable RAM so it is callable from an
-// ISR even while flash is busy (XIP stall, OTA, logger flash write).
-// Each family uses a section its stock linker already routes to RAM:
-// RTL8710B → .image2.ram.text, RTL8720C → .sram.text. LN882H is the
-// exception: its stock linker has no matching glob, so patch_linker.py
-// injects KEEP(*(.sram.text*)) into .flash_copysection at pre-link.
+// ISR even while flash is busy (XIP stall, OTA, logger flash write). All
+// LibreTiny families that need it share the same .sram.text input section
+// name; how that section is routed into RAM differs per family:
+//   RTL8720C: stock linker consumes *(.sram.text*) into .ram.code_text.
+//   RTL8710B: patch_linker.py.script injects KEEP(*(.sram.text*)) at the
+//             top of .ram_image2.data (which IS in ltchiptool's
+//             sections_ram). The stock linker has KEEP(*(.image2.ram.text*))
+//             in .ram_image2.text but that output section is NOT in
+//             ltchiptool's AmebaZ elf2bin sections_ram list, so code routed
+//             there is dropped from the flashed binary.
+//   LN882H:   patch_linker.py.script injects KEEP(*(.sram.text*)) into
+//             .flash_copysection (> RAM0 AT> FLASH), after KEEP(*(.vectors))
+//             so the Cortex-M4 vector table stays 512-byte-aligned for VTOR.
 //
 // BK72xx (all variants) are left as a no-op: their SDK wraps flash
 // operations in GLOBAL_INT_DISABLE() which masks FIQ + IRQ at the CPU for
@@ -26,13 +34,7 @@
 // layer.
 #if defined(USE_BK72XX)
 #define IRAM_ATTR
-#elif defined(USE_LIBRETINY_VARIANT_RTL8710B)
-// Stock linker consumes *(.image2.ram.text*) into .ram_image2.text (> BD_RAM).
-#define IRAM_ATTR __attribute__((noinline, section(".image2.ram.text")))
 #else
-// RTL8720C: stock linker consumes *(.sram.text*) into .ram.code_text.
-// LN882H: patch_linker.py.script injects *(.sram.text*) into
-// .flash_copysection (> RAM0 AT> FLASH).
 #define IRAM_ATTR __attribute__((noinline, section(".sram.text")))
 #endif
 #define PROGMEM
diff --git a/esphome/components/libretiny/patch_linker.py.script b/esphome/components/libretiny/patch_linker.py.script
index 3a8a4787ed..dfeaaa57d1 100644
--- a/esphome/components/libretiny/patch_linker.py.script
+++ b/esphome/components/libretiny/patch_linker.py.script
@@ -6,12 +6,18 @@ import re
 import subprocess
 
 # ESPHome marks ISR code IRAM_ATTR, which on LibreTiny maps to a per-family
-# section routed into RAM-executable memory (see esphome/core/hal.h).
+# section routed into RAM-executable memory (see esphome/core/hal.h). The
+# input section name is always .sram.text; only the output section it lands
+# in differs per family.
 #
 # This script is NOT loaded on BK72xx (IRAM_ATTR is a no-op there; the SDK
 # masks FIQ+IRQ around flash writes). On the remaining families:
-# - RTL8710B: hal.h uses section(".image2.ram.text"); stock linker consumes it.
-# - RTL8720C: hal.h uses section(".sram.text"); stock linker consumes it.
+# - RTL8720C: stock linker consumes *(.sram.text*) into .ram.code_text.
+# - RTL8710B: stock linker has KEEP(*(.image2.ram.text*)) in .ram_image2.text,
+#   but ltchiptool's AmebaZ elf2bin (soc/ambz/binary.py) does NOT list
+#   .ram_image2.text in sections_ram, so code there is silently dropped from
+#   the flashed image. Inject KEEP(*(.sram.text*)) at the top of
+#   .ram_image2.data (which IS extracted) instead.
 # - LN882H: stock linker has no glob for ".sram.text", so we inject
 #   KEEP(*(.sram.text*)) into ".flash_copysection" (> RAM0 AT> FLASH)
 #   immediately after KEEP(*(.vectors)), so the vector table stays at
@@ -34,6 +40,20 @@ _KEEP_LINE = (
 # aligned address; injecting before the vectors would push them to an
 # unaligned offset and mis-route every IRQ handler.
 _LN_COPY = re.compile(r"(KEEP\(\*\(\.vectors\)\)[^\n]*\n)")
+# Inject at the top of .ram_image2.data, before __data_start__ so our code
+# does not fall inside the data range markers. .ram_image2.data is one of the
+# sections ltchiptool's AmebaZ elf2bin extracts; BD_RAM is rwx so the code is
+# executable. AmbZ has no C runtime .data copy loop (the bootloader loads
+# image2 into BD_RAM whole) so the inline code is not clobbered after boot.
+#
+# The regex is intentionally strict (no attribute / ALIGN between the section
+# name and the opening brace, brace on its own line). If a future AmbZ SDK
+# linker template changes this format, _pre_link raises RuntimeError on the
+# unpatched .ld file(s), and the RTL8710B CI compile job in
+# tests/test_build_components fails on the PR, surfacing the mismatch loudly
+# rather than silently shipping a binary with IRAM_ATTR code dropped from
+# one or both OTA slots.
+_AMBZ_DATA = re.compile(r"(\.ram_image2\.data\s*:\s*\n?\s*\{\s*\n)")
 
 
 def _detect(env):
@@ -71,12 +91,11 @@ def _inject_keep(host_section):
 
 
 # Variants not listed here intentionally have no .ld patcher:
-# - RTL8710B: hal.h uses section(".image2.ram.text") which the stock linker
-#   already routes into .ram_image2.text (> BD_RAM).
-# - RTL8720C: stock linker already consumes *(.sram.text*).
+# - RTL8720C: stock linker already consumes *(.sram.text*) into .ram.code_text.
 # - BK72xx (all): SDK masks FIQ+IRQ around flash writes, IRAM_ATTR is no-op.
 _PATCHERS_BY_VARIANT = {
     "LN882H": (_inject_keep(_LN_COPY),),
+    "RTL8710B": (_inject_keep(_AMBZ_DATA),),
 }
 
 
@@ -87,13 +106,14 @@ def _patchers_for(variant):
 def _pre_link(target, source, env):
     build_dir = env.subst("$BUILD_DIR")
     ld_files = [f for f in os.listdir(build_dir) if f.endswith(".ld")]
-    patched = 0
+    patched = []
+    unpatched = []
     for name in ld_files:
         path = os.path.join(build_dir, name)
         with open(path, "r", encoding="utf-8") as fh:
             original = fh.read()
         if _MARKER in original:
-            patched += 1
+            patched.append(name)
             continue
         content = original
         for fn in _patchers:
@@ -102,7 +122,9 @@ def _pre_link(target, source, env):
             with open(path, "w", encoding="utf-8") as fh:
                 fh.write(content)
             print("ESPHome: patched {} for IRAM_ATTR placement".format(name))
-            patched += 1
+            patched.append(name)
+        else:
+            unpatched.append(name)
     if not patched:
         raise RuntimeError(
             "ESPHome: no .ld in {} was patched for IRAM_ATTR. Update the "
@@ -110,6 +132,20 @@ def _pre_link(target, source, env):
                 build_dir
             )
         )
+    # Every .ld in the build must be patched. RTL8710B generates one .ld per
+    # OTA slot (xip1, xip2); if only one matches, the unpatched slot would
+    # ship with IRAM_ATTR code dropped to zeros and brick the device on the
+    # boot after an OTA into that slot.
+    if unpatched:
+        raise RuntimeError(
+            "ESPHome: {} of {} .ld file(s) in {} were not patched for "
+            "IRAM_ATTR: {}. The regex in patch_linker.py.script "
+            "(_PATCHERS_BY_VARIANT[{!r}]) matched the others but not "
+            "these. Update the regex to cover all linker scripts.".format(
+                len(unpatched), len(ld_files), build_dir,
+                ", ".join(unpatched), _variant,
+            )
+        )
 
 
 # Substrings matched against demangled names as a fallback on RTL8720C,