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J. Nick Koston
867fae3bb8
Switch writer-side plain stores under lock_ to __atomic_store_n with __ATOMIC_RELAXED on NO_ATOMICS. The input value for RMW is read plainly (safe — only writers mutate, serialised by the lock; readers only atomic-load so two reads don't race). Closes the formal C++ memory-model hole where plain-store vs atomic-load was a data race in the standard even though aligned 32-bit STR/LDR on ARMv5TE is atomic in practice. Applies to scheduler.h counter mutators and the under-lock writes to last_millis / millis_major in time_64.cpp's near-rollover branch. Same ARMv5TE codegen (plain STR). ATOMICS / SINGLE paths unchanged.
