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J. Nick Koston
3c2396ab86
Same treatment as the scheduler counters (#15947): - Unlocked reads of millis_major / last_millis at the top of Millis64Impl::compute(): switch from plain reads to __atomic_load_n(&..., __ATOMIC_RELAXED). - Unlocked write of last_millis in the "normal forward progression" branch: switch from plain assignment to __atomic_store_n(..., __ATOMIC_RELAXED). This is the one write that happens without the lock, so it needs to be formally atomic to pair cleanly with the unlocked atomic reader in the C++ memory model. - Writes under `lock` stay plain (millis_major++, last_millis = now inside the near-rollover branch). The lock serialises them against other writers. On ARMv5TE the builtins compile to plain LDR/STR — same codegen, no libatomic dependency. Updates the "accepting minor races" comment to describe the formally-defined version of the race.
