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J. Nick Koston
22ed9b3c1e
Copilot review on #15947 flagged that `volatile uint32_t` is not a well-defined concurrent access in the C++ memory model — it prevents the compiler caching/eliding the read, but does not turn a plain cross-thread read/write pair into a defined access. Technically still a formal data race even though aligned 32-bit LDR/STR on ARMv5TE is atomic at the hardware level. Switch the NO_ATOMICS counter reads and writes to GCC's atomic builtins with __ATOMIC_RELAXED: - Readers: __atomic_load_n(&counter, __ATOMIC_RELAXED) - Writers (under lock_): __atomic_store_n(&counter, new_value, __ATOMIC_RELAXED) - Increment/decrement (under lock_): explicit load + compute + __atomic_store_n. Lock_ serialises the load-modify-store against other writers; the atomic ops make the write visible to concurrent readers in the memory model. On ARMv5TE these builtins compile to plain LDR/STR — same codegen as the previous volatile approach, and no libatomic dependency (only RMW builtins like __atomic_fetch_add would need the lib). ATOMICS and SINGLE paths are unchanged.
