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[pulse_counter] Fix compilation on ESP32-C6/C5/H2/P4

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SOC_MOD_CLK_APB does not exist in the soc_module_clk_t enum on
ESP32-C6, C5, H2, and P4 variants. Revert to esp_clk_apb_freq()
which works on all variants and is the same function the ESP-IDF
PCNT driver uses internally for glitch filter calculation.
This commit is contained in:
J. Nick Koston
2026-02-18 18:39:35 -06:00
parent bd055e75b9
commit 9dd62b8c34
1 changed files with 2 additions and 4 deletions
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esphome/components/pulse_counter/pulse_counter_sensor.cpp
+2 -4
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@@ -2,7 +2,7 @@
#include "esphome/core/log.h"
#ifdef HAS_PCNT
#include <esp_clk_tree.h>
#include <esp_private/esp_clk.h>
#include <hal/pcnt_ll.h>
#endif
@@ -117,9 +117,7 @@ bool HwPulseCounterStorage::pulse_counter_setup(InternalGPIOPin *pin) {
}
if (this->filter_us != 0) {
uint32_t apb_freq;
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_APB, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &apb_freq);
uint32_t max_glitch_ns = PCNT_LL_MAX_GLITCH_WIDTH * 1000000u / apb_freq;
uint32_t max_glitch_ns = PCNT_LL_MAX_GLITCH_WIDTH * 1000000u / (uint32_t) esp_clk_apb_freq();
pcnt_glitch_filter_config_t filter_config = {
.max_glitch_ns = std::min(this->filter_us * 1000u, max_glitch_ns),
};