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[mipi_spi] Fix reversion in dc/cs sequence for spi_16 (#19745)

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This commit is contained in:
Clyde Stubbs
2026-09-27 10:04:17 -04:00
committed by GitHub
parent b1d07759e2
commit 97f362a718
1 changed files with 8 additions and 8 deletions
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esphome/components/mipi_spi/mipi_spi.h
+8 -8
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@@ -246,20 +246,18 @@ class MipiSpi : public display::Display,
this->write_cmd_addr_data(8, 0x02, 24, cmd << 8, bytes, len);
this->disable();
} else if constexpr (BUS_TYPE == BUS_TYPE_OCTAL) {
// Toggle D/C only while holding the bus; on boards where D/C doubles as
// another bus signal, driving it while another device owns the bus
// corrupts that device's transfer.
this->enable();
this->dc_pin_->digital_write(false);
this->write_cmd_addr_data(0, 0, 0, 0, &cmd, 1, 8);
this->dc_pin_->digital_write(true);
this->disable();
// hold the bus between command and data to avoid a glitch on the D/C line
if (len != 0) {
this->enable();
this->write_cmd_addr_data(0, 0, 0, 0, bytes, len, 8);
this->disable();
}
this->disable();
} else if constexpr (BUS_TYPE == BUS_TYPE_SINGLE) {
// Toggle D/C only while holding the bus; works around a quirk in the CoreS3 and W5500 ethernet combination.
// See https://github.com/esphome/esphome/pull/18529
this->enable();
this->dc_pin_->digital_write(false);
this->write_byte(cmd);
@@ -271,12 +269,14 @@ class MipiSpi : public display::Display,
this->disable();
}
} else if constexpr (BUS_TYPE == BUS_TYPE_SINGLE_16) {
this->enable();
// DC must be stable before CS as the clock is gated by CS
this->dc_pin_->digital_write(false);
this->enable();
this->write_byte(cmd);
this->dc_pin_->digital_write(true);
this->disable();
this->dc_pin_->digital_write(true);
for (size_t i = 0; i != len; i++) {
// must enable and disable for each byte based on empirical testing
this->enable();
this->write_byte(0);
this->write_byte(bytes[i]);