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78 lines
3.6 KiB
C++
78 lines
3.6 KiB
C++
#include <gtest/gtest.h>
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#include "../common.h"
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#include "esphome/components/epaper_spi/epaper_spi_t133a01.h"
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namespace esphome::epaper_spi::testing {
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/// Exposes the protected transfer machinery so the yield behaviour can be driven directly.
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class TestableT133A01 : public EPaperT133A01 {
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public:
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TestableT133A01(uint16_t width, uint16_t height) : EPaperT133A01("test", width, height, nullptr, 0) {}
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void install(spi::SPIDelegate *delegate) {
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this->delegate_ = delegate;
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this->set_dc_pin(&this->dc);
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this->set_cs_pins(&this->cs, &this->cs1);
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ASSERT_TRUE(this->init_buffer_(this->buffer_length_));
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}
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using EPaperT133A01::transfer_data;
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RecordingPin dc, cs, cs1;
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};
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/// Regression test for the T133A01 transfer deadlock (issue #17668).
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///
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/// `transfer_data()` evaluates its yield deadline *after* incrementing the row counter, so the
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/// deadline can expire on a phase's final row. The phase is then complete but the function
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/// reports "not done"; on the next call the phase guard is false, so the `disable()` /
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/// CS-deassert epilogue is skipped permanently. The SPI transaction is never closed and the
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/// next `enable()` blocks forever, tripping the task watchdog.
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///
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/// Here the CS phase is two rows and every row write overruns the deadline, so the second call
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/// completes the phase exactly as the deadline expires, which is the failing alignment. The completed
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/// phase must still run its epilogue: end the transaction and deassert CS.
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TEST(EPaperT133A01, CompletedPhaseRunsEpilogueWhenDeadlineExpiresOnFinalRow) {
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// width 8 -> 4 bytes per row, 2 per half-row; height 2 -> a two-row CS phase
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TestableT133A01 display(8, 2);
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TimedSPIDelegate delegate(MAX_TRANSFER_TIME + 5);
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display.install(&delegate);
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// First call performs the one-off CCSET setup (which opens and closes a transaction of its
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// own) and then writes row 0 of the CS phase before yielding on the deadline.
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ASSERT_FALSE(display.transfer_data()) << "transfer should have yielded after the first row";
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ASSERT_FALSE(display.cs.level) << "CS must stay asserted across a yield mid-phase";
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const int closed_after_setup = delegate.end_count;
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// Second call writes the final row of the CS phase; the deadline expires as it lands.
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display.transfer_data();
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EXPECT_EQ(delegate.end_count, closed_after_setup + 1)
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<< "completed CS phase skipped disable() -- SPI transaction left open";
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EXPECT_TRUE(display.cs.level) << "completed CS phase left CS asserted";
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}
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/// The CS1 phase has the same off-by-one, but fails worse: after the skipped epilogue the
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/// function falls through to `return true`, reporting the transfer complete while the SPI
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/// transaction is still open and CS1 is still asserted. The next command's `enable()` then
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/// blocks forever. A transfer that reports done must have released the bus.
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TEST(EPaperT133A01, TransferReportsDoneOnlyAfterReleasingTheBus) {
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TestableT133A01 display(8, 2);
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TimedSPIDelegate delegate(MAX_TRANSFER_TIME + 5);
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display.install(&delegate);
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// Both phases are two rows each and every row overruns the deadline, so the transfer needs
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// one call per row plus the setup call. Bound the loop so a regression fails rather than hangs.
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int calls = 0;
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while (!display.transfer_data()) {
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ASSERT_LT(++calls, 10) << "transfer never reported completion";
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}
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EXPECT_TRUE(display.cs1.level) << "transfer reported done with CS1 still asserted";
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EXPECT_EQ(delegate.begin_count, delegate.end_count)
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<< "transfer reported done with an SPI transaction still open -- the next enable() would deadlock";
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}
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} // namespace esphome::epaper_spi::testing
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