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esphome
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417fdd9dc76ef0a5a29e151cbf32a43e10d068c1
esphome
/
tests
/
component_tests
/
uart
T
History
Max Slotov
645144ad4d
[uart] Validate parity and stop bits correctly (
#20161
)
2026-10-05 13:21:48 +11:00
..
config
[uart] Skip the parity setter when it matches the default (
#20069
)
2026-10-05 12:12:34 +13:00
test_clock_source.py
[uart] clock_source option (
#16486
)
2026-09-24 15:16:40 +01:00
test_final_validate.py
[uart] Validate parity and stop bits correctly (
#20161
)
2026-10-05 13:21:48 +11:00
test_parity.py
[uart] Skip the parity setter when it matches the default (
#20069
)
2026-10-05 12:12:34 +13:00
