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c3233739c5
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com> Co-authored-by: pre-commit-ci-lite[bot] <117423508+pre-commit-ci-lite[bot]@users.noreply.github.com> Co-authored-by: tomaszduda23 <tomaszduda23@gmail.com>
56 lines
1.6 KiB
YAML
56 lines
1.6 KiB
YAML
# P0.2, P0.4 and P0.5 all live on the same Zephyr port device (gpio0) and each
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# attaches its own interrupt. This locks in shared-port behavior: every pin owns
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# a separate gpio_callback initialized with its own BIT(pin) mask, so Zephyr
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# dispatches to each pin independently even though the port device is shared.
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binary_sensor:
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- platform: gpio
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pin: 2
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id: gpio_binary_sensor
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use_interrupt: true
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interrupt_type: ANY
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# Inverted pin with an edge-specific interrupt: exercises the inversion-aware
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# interrupt-arming path (logical RISING must arm on the physical falling edge).
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- platform: gpio
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pin:
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number: P0.4
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inverted: true
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id: gpio_binary_sensor_inverted
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use_interrupt: true
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interrupt_type: RISING
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# Second non-inverted interrupt on the same port (gpio0) as P0.2 above: verifies
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# multiple pins sharing one port device each get their own callback/pin_mask.
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- platform: gpio
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pin: P0.5
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id: gpio_binary_sensor_shared_port
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use_interrupt: true
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interrupt_type: FALLING
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output:
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- platform: gpio
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pin: P0.3
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id: gpio_output
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switch:
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- platform: gpio
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pin: P1.2
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id: gpio_switch
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- platform: gpio
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pin: P1.3
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id: gpio_switch_interlock_1
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interlock: [gpio_switch_interlock_2, gpio_switch_interlock_3]
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interlock_wait_time: 100ms
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- platform: gpio
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pin: P1.4
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id: gpio_switch_interlock_2
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interlock: [gpio_switch_interlock_1, gpio_switch_interlock_3]
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- platform: gpio
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pin: P1.5
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id: gpio_switch_interlock_3
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interlock: [gpio_switch_interlock_1, gpio_switch_interlock_2]
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interlock_wait_time: 50ms
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