From dd861ab9b647efe1413e66ccb108efd5e7deeb4d Mon Sep 17 00:00:00 2001 From: "J. Nick Koston" Date: Thu, 4 Sep 2025 15:51:28 -0500 Subject: [PATCH] align --- esphome/components/max6956/max6956.cpp | 10 +++++----- esphome/components/max6956/max6956.h | 16 ++++++++-------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/esphome/components/max6956/max6956.cpp b/esphome/components/max6956/max6956.cpp index b3b9c35c77..0b2fdec34f 100644 --- a/esphome/components/max6956/max6956.cpp +++ b/esphome/components/max6956/max6956.cpp @@ -54,12 +54,12 @@ bool MAX6956::digital_read_hw(uint8_t pin) { // Calculate bank index based on the base class view (no offset adjustment) uint8_t bank_index = pin / MAX6956_BANK_SIZE; - // Register addresses aligned with base class banks + // Use the named constants for register addresses static const uint8_t bank_regs[4] = { - 0x40, // Bank 0: 4 ports 4-7 (bits D0-D3, D4-D7 read as 0) - 0x48, // Bank 1: 8 ports 8-15 (bits D0-D7) - 0x50, // Bank 2: 8 ports 16-23 (bits D0-D7) - 0x58, // Bank 3: 8 ports 24-31 (bits D0-D7) + MAX6956_4PORTS_4_7, // Bank 0: 4 ports 4-7 (bits D0-D3, D4-D7 read as 0) + MAX6956_8PORTS_8_15, // Bank 1: 8 ports 8-15 (bits D0-D7) + MAX6956_8PORTS_16_23, // Bank 2: 8 ports 16-23 (bits D0-D7) + MAX6956_8PORTS_24_31, // Bank 3: 8 ports 24-31 (bits D0-D7) }; // Read the appropriate register diff --git a/esphome/components/max6956/max6956.h b/esphome/components/max6956/max6956.h index f37f04bd5f..3bfed4c500 100644 --- a/esphome/components/max6956/max6956.h +++ b/esphome/components/max6956/max6956.h @@ -30,14 +30,14 @@ enum MAX6956GPIORegisters { MAX6956_CONFIGURATION = 0x04, MAX6956_TRANSITION_DETECT_MASK = 0x06, MAX6956_DISPLAY_TEST = 0x07, - MAX6956_PORT_CONFIG_START = 0x09, // Port Configuration P7, P6, P5, P4 - MAX6956_CURRENT_START = 0x12, // Current054 - MAX6956_1PORT_VALUE_START = 0x20, // Port 0 only (virtual port, no action) - MAX6956_8PORTS_VALUE_START = 0x44, // 8 ports 4-11 (data bits D0-D7) - // Additional 8-port bulk read registers - MAX6956_8PORTS_12_19 = 0x4C, // 8 ports 12-19 - MAX6956_8PORTS_20_27 = 0x54, // 8 ports 20-27 - MAX6956_8PORTS_24_31 = 0x58, // 8 ports 24-31 + MAX6956_PORT_CONFIG_START = 0x09, // Port Configuration P7, P6, P5, P4 + MAX6956_CURRENT_START = 0x12, // Current054 + MAX6956_1PORT_VALUE_START = 0x20, // Port 0 only (virtual port, no action) + // 8-port bulk read registers aligned with base class banks + MAX6956_4PORTS_4_7 = 0x40, // 4 ports 4-7 (bits D0-D3, D4-D7 read as 0) + MAX6956_8PORTS_8_15 = 0x48, // 8 ports 8-15 (bits D0-D7) + MAX6956_8PORTS_16_23 = 0x50, // 8 ports 16-23 (bits D0-D7) + MAX6956_8PORTS_24_31 = 0x58, // 8 ports 24-31 (bits D0-D7) }; enum MAX6956GPIOFlag { FLAG_LED = 0x20 };