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@@ -14,9 +14,8 @@ namespace {
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// 80 MHz ESP8266 clock
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constexpr uint32_t CPU_HZ = 80000000;
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// Drives a SoftwareSerialRxDecoder with a simulated line: frames are turned into
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// edges at their ideal cycle counts (plus optional jitter), and the main loop is
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// emulated by poll(), which finalizes a pending byte and drains the buffer.
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// Simulated line: frames become edges at ideal cycle counts plus jitter;
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// poll() emulates the main loop (finalize pending byte, drain buffer).
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class LineSim {
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public:
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LineSim(uint32_t baud, uint8_t data_bits, bool parity, bool odd, uint8_t stop_bits, size_t buffer_size = 64)
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@@ -45,8 +44,7 @@ class LineSim {
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this->received_.push_back(this->dec_.read_byte());
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}
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// Emit one frame starting at cycle `start`; `jitter` is the per edge offset in cycles
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// (positive or negative) supplied by the caller. Returns the cycle at which the frame ends.
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// Emit one frame at `start` with per edge `jitter` in cycles; returns the end cycle.
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uint32_t send(
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uint8_t value, uint32_t start, const std::function<int32_t()> &jitter = [] { return 0; }) {
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std::vector<bool> bits;
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@@ -123,8 +121,7 @@ TEST(SoftwareSerialRxDecoder, DecodesBackToBackFramesAtCommonBaudRates) {
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}
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TEST(SoftwareSerialRxDecoder, ToleratesEdgeJitterUpToAQuarterBit) {
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// Consecutive edges can each be off by up to a quarter bit in either direction,
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// so the measured run length is within half a bit of the true one.
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// A quarter bit per edge keeps each run within the half bit rounding budget.
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run_stream({9600, 8, false, false, 1}, 0.24, 0, 2000, 1);
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run_stream({9600, 8, false, false, 1}, 0.24, 7, 2000, 2);
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run_stream({38400, 8, false, false, 1}, 0.24, 4, 2000, 3);
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@@ -141,11 +138,10 @@ TEST(SoftwareSerialRxDecoder, AllOnesByteCompletesOnlyByFinalize) {
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LineSim sim(9600, 8, false, false, 1);
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const uint32_t bit = sim.bit_cycles();
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uint32_t t = 5000;
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// Start bit, then the line goes high and stays there: 0xFF has no closing edge.
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// 0xFF: start bit, then the line stays high with no closing edge.
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sim.edge(t, false);
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sim.edge(t + bit, true);
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EXPECT_TRUE(sim.decoder().pending());
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// Eight data bits plus the stop bit must elapse after the rising edge.
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sim.poll(t + bit + 8 * bit);
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EXPECT_TRUE(sim.received().empty());
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EXPECT_FALSE(sim.decoder().finalize_due(t + bit + 8 * bit));
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@@ -191,9 +187,7 @@ TEST(SoftwareSerialRxDecoder, BreakConditionIsDroppedAndResyncs) {
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TEST(SoftwareSerialRxDecoder, CollapsedEdgeIsIgnoredAndStreamRealignsAtIdle) {
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LineSim sim(9600, 8, false, false, 1);
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const uint32_t bit = sim.bit_cycles();
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// 0x31 = 0b00110001: start, 1, 0, 0, 0, 1, 1, 0, 0, stop. Lose the rising edge
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// of data bit 4 (ISR delayed past two edges), so the next edge arrives at the
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// same level as the last one the decoder saw.
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// 0x31: lose the rising edge of bit 4, so the next edge repeats the last level.
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uint32_t t = 5000;
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sim.edge(t, false); // start
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sim.edge(t + 1 * bit, true); // bit0 = 1
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@@ -220,8 +214,7 @@ TEST(SoftwareSerialRxDecoder, DropsBytesWhenBufferIsFullAndKeepsOldest) {
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}
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TEST(SoftwareSerialRxDecoder, SetupAgainDropsStaleStateAndUsesNewBufferAndFraming) {
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// Mirrors load_settings(): bytes buffered and a frame left open under 8N1 in a
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// 64 byte buffer, then setup() again with 5E2 in a 4 byte buffer.
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// Mirrors load_settings(): buffered 8N1 bytes and an open frame, then setup() as 5E2.
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LineSim sim(9600, 8, false, false, 1);
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uint32_t t = 5000;
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for (int n = 0; n < 10; n++)
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@@ -237,8 +230,7 @@ TEST(SoftwareSerialRxDecoder, SetupAgainDropsStaleStateAndUsesNewBufferAndFramin
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EXPECT_FALSE(dec.pending());
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EXPECT_EQ(dec.read_byte(), 0);
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// 5E2 frames fed straight into the reconfigured decoder: capacity is 3, the
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// rest are dropped and nothing is written past the end of the new buffer.
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// Capacity of the 4 byte buffer is 3; the spare slot must stay untouched.
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auto send_5e2 = [&](uint8_t value, uint32_t start) {
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bool line = true;
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uint32_t at = start;
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