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[core] address review polish on main-loop decoupling
Doc and test updates from a code review of this PR: - Correct the `tail_us == 0 on Phase A-only ticks` claim in the Application::loop() comment and the RuntimeStatsCollector::record_loop_active docstring. `loop_tail_start_us` is set to `loop_before_end_us`, and `loop_now_us` is sampled later, so `tail_us` on Phase A-only ticks is the small gate-check + record prefix — tiny but non-zero. (Also flagged by Copilot on application.h:623 and runtime_stats.h:45.) - Call out ESP8266 as the floor case in the WDT_FEED_INTERVAL_MS margin table. Its soft WDT (~1.6 s) is the tightest margin at ~5x, so future changes to the constant need to preserve comfortable headroom there. - Tighten the test lower bound at tests/integration/test_loop_interval_decoupling.py from `2 <= loop_delta <= 6` to `3 <= loop_delta <= 6`. Allowing 2 would let a >50% slowdown from the 4-in-2s nominal pass as CI jitter, which undermines the regression signal. 3 keeps the test honest while still absorbing realistic CI jitter. - Add a second integration test (test_loop_interval_default_not_pulled_forward) that covers the inverse direction: at the default loop_interval_ with a fast scheduler item (5 ms — well under the old delay_time/2 = 8 ms floor), the component phase must still run at ~62 Hz, not the pre-fix ~128 Hz. This locks down the original 128 Hz → 62 Hz regression that motivated the PR.
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@@ -58,7 +58,9 @@ async def test_loop_interval_decoupling(
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# Component phase should fire ~4 times in 2s. The upper bound must be
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# less than 8: the pre-decoupling behavior clamped to ~250ms cadence
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# giving ~8 loops/2s, so allowing 8 would let the old behavior pass.
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assert 2 <= loop_delta <= 6, (
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# Lower bound 3 (not 2) keeps the test honest: a >30% slowdown from
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# the ~4 nominal is not normal CI jitter and should fail.
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assert 3 <= loop_delta <= 6, (
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f"Component loop should fire ~4 times in 2s at loop_interval=500ms, "
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f"got {loop_delta}"
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)
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