From 21c32966ee0230a020a96cbf72630451e0161d4c Mon Sep 17 00:00:00 2001 From: "J. Nick Koston" Date: Wed, 15 Apr 2026 16:11:50 -1000 Subject: [PATCH] =?UTF-8?q?libretiny:=20fix=20hal.h=20intro=20comment=20?= =?UTF-8?q?=E2=80=94=20only=20LN882H=20uses=20the=20patcher?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- esphome/core/hal.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/esphome/core/hal.h b/esphome/core/hal.h index a0e13ef3c7..e4083622b9 100644 --- a/esphome/core/hal.h +++ b/esphome/core/hal.h @@ -25,10 +25,10 @@ // IRAM_ATTR places a function in executable RAM so it is callable from an // ISR even while flash is busy (XIP stall, OTA, logger flash write). -// patch_linker.py.script routes ".sram.text" into each family's RAM- -// executable output section: .ram_image2.text on RTL8710B, -// .flash_copysection on LN882H; RTL8720C's stock linker already consumes -// *(.sram.text*) via its .ram.code_text output. +// Each family uses a section its stock linker already routes to RAM: +// RTL8710B → .image2.ram.text, RTL8720C → .sram.text. LN882H is the +// exception: its stock linker has no matching glob, so patch_linker.py +// injects KEEP(*(.sram.text*)) into .flash_copysection at pre-link. // // BK72xx (all variants) are left as a no-op: their SDK wraps flash // operations in GLOBAL_INT_DISABLE() which masks FIQ + IRQ at the CPU for